Performance and area optimization methods in compiler for a dynamically reconfigurable processor
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Date
2011-09-21
Authors
Journal Title
Journal ISSN
Volume Title
Publisher
慶應義塾大学理工学研究科
Abstract
Description
博士（工学）, 2011, 開放環境科学
Keywords
動的再構成プロセッサ, 疎粒度再構成アーキテクチャ, 動作合成, パイプライン化, 配線遅延, dynamically reconfigurable processor, coarse-grained reconfigurable architecture, high-level synthesis, pipelining, wire delay